1. Field of the Invention
The present invention relates to a liquid crystal display and, more particularly, to a thin film transistor array substrate of a liquid crystal display which is provided with a modified connection region to allow an automatic separation of gate lines from a shorting bar.
2. Discussion of Related Art
An anodizing process is a process for growing an oxide layer on the surface of a metal by submerging the metal in an electrolytic solution. A positive (+) power is then applied to the metal, while a negative (-) power is applied to another metal, e.g., platinum, or the like. This technique is carried out to form a gate insulating layer on gate electrodes and gate lines, which are patterned during the fabrication of a liquid crystal display.
A shorting bar is a metal pattern for connecting the gate lines to an external power source and applying electric power to them so as to cause an anodization of the gate lines and the gate electrodes connected to the gate lines. After the fabrication of the liquid crystal display is completed, the shorting bar must be separated from the gate line in order to examine and operate the finished liquid crystal display.
FIGS. 1A, 1B and 1C illustrate the configuration of a plurality of gate lines 12L and a shorting bar 18 in a conventional liquid crystal display. FIG. 1A shows the arrangement before an anodizing process, FIG. 1B shows the arrangement after the anodizing process, and FIG. 1C shows the arrangement after a cutting process using a laser.
As shown in FIG. 1A, a plurality of gate lines 12L are arranged on a substrate and each of the gate lines 12L is connected to a shorting bar 18. In an anodizing process, external power is applied to the respective gate lines 12L via the shorting bar 18.
Before the anodizing process, each gate line 12L is connected to the shorting bar 18 by a connection region C. Hereinafter, the portion of the gate line connected to the shorting bar is referred to as "connection region". This connection region has the same width as the rest of the gate line 12L in the conventional liquid crystal display.
When the substrate having the above connections is submerged in an electrolytic solution to carry out an anodizing process, an anodic oxide layer 13 is formed to have a predetermined width on the lateral sides of the gate lines 12L and the shorting bar 18, as shown in FIG. 1B. The gate lines 12L remain in connection with the shorting bar 18 after the anodizing process.
When the substrate is finished, it is necessary to cut the connection regions C between the gate lines 12L and the shorting bar 18, as shown in FIG. 1C.
FIGS. 2A to 2F illustrate a process for fabricating the conventional liquid crystal display which includes an anodizing step. Each figure shows two portions of the thin film transistor array substrate of the liquid crystal display device. The left side shows a thin film transistor, and the right side shows a connection region between a gate line and a shorting bar. The connection region is shown in a cross-sectional view taken along the line II--II in FIG. 1C.
Referring to FIG. 2A, a polysilicon layer is formed on an insulating substrate 100 and is patterned by photolithography to form an active layer 11. The polysilicon layer is formed by depositing an amorphous silicon layer and applying a laser beam to crystallize the amorphous silicon layer. An alternative method is to deposit polysilicon at a low temperature. To prevent any impurities contained in the substrate from penetrating into the active layer made of polysilicon, it is desirable to form a buffer layer by depositing an insulating material, such as silicon oxide or silicon nitride, before the polysilicon layer is formed. A gate insulating layer 110 is then formed on the whole surface by depositing an insulating material such as silicon oxide or the like.
As shown in FIG. 2B, a metal layer, such as Al or the like, which can be anodized, and a photoresist layer are sequentially formed on the gate insulating layer 110. The photoresist layer is patterned by lithography to form a photoresist pattern 19, the metal layer is etched using the photoresist pattern 19 as a mask to form a gate electrode 12G, a gate line 12L extending from the gate electrode 12G, and a shorting bar 18. Accordingly, the gate electrode 12G, the gate line 12L, and the shorting bar 18 are made of the same metal material. The gate line 12L is connected with the shorting bar 18. The photoresist pattern 19 remains on the metal pattern of the gate electrode 12G, the gate line 12L extending from the gate electrode 12G, and the shorting bar 18.
As shown in FIG. 2C, the substrate is immersed into an electrolytic solution to carry out an anodizing process. As a result, an anodic oxide layer 13, having a predetermined thickness, is formed on the lateral sides of the metal pattern.
As shown in FIG. 2D, after the photoresist pattern 19 is removed, the gate insulating layer 110 is patterned by photolithography using the gate electrode 12G and the anodic oxide layer 13 formed on the lateral sides of the gate electrode 12G as a mask to expose a part of the active layer 11.
An n.sup.+ -type layer is formed in the exposed portion of the active layer 11 by heavily doping the entire surface with impurities of n.sup.+ conductivity type. The n.sup.+ -type layer becomes a source region 14S and a drain region 14D. The active layer under the gate electrode 12G becomes a channel region 11C. The portions between the source region 14S and the channel region 11C and between the drain region 14D and the channel region 11C become offset regions 15.
As shown in FIG. 2E, an insulating interlayer 120 is formed by depositing an insulating material, such as silicon oxide or the like, on the entire surface. Portions of the insulating interlayer 120 are removed by photolithography to form contact holes exposing the source and drain regions 14S and 14D.
Subsequently, a conductive material, such as Cr or the like, is deposited on the entire surface and is patterned by photolithography to form a source electrode 16S connected to the source region 14S and a drain electrode 16D connected to the drain region 14D.
Then, a protective layer 130 is formed by depositing an insulating material on the entire surface. A portion of the protective layer 130 is removed by photolithography to form a contact hole exposing a part of the drain electrode 16D.
Then, a transparent conductive layer is formed by sputtering on the entire surface and is patterned by photolithography to form a pixel electrode 17 connected to the drain electrode 16D.
As shown in FIG. 2F, the connection region C, located between the shorting bar 18 and the gate line 12L, is cut by photo-etching or by a laser beam so as to allow for testing of the finished substrate.
The process of cutting the connection region C between the shorting bar 18 and the gate line 12L is carried out in the final stage of fabrication, but it can be better accomplished after the anodizing process as a matter of convenience.
As described above, an additional process is required for severing the connections between the gate lines and the shorting bar for the purpose of testing the device. This additional step is necessary because the gate line is typically around 10 .mu.m in width while the anode oxide layer is grown up to a width of 1-1.5 .mu.m at most. Elimination of this step would simplify the manufacturing process.